Constraint Conflict Resolution
Log documenting a geometric constraint conflict between current capacity track width and electrical isolation clearances, and the trade-off matrix used to resolve it.
- — 01 Evidence is required. Assumptions are temporary.
- — 04 Traceability by default.
Issue
During the layout routing of the motor driver board, the co-design pipeline flagged a persistent double-check violation in the routing channel between the high-current power stage and the low-voltage analog feedback signal lanes. The physical space was insufficient to satisfy both current-carrying trace widths and safety electrical spacing.
Requirements
- Requirement A (Current Capacity): The power rail trace must sustain 12A continuous current. Standard solver calculations for 1 oz (35µm) copper specify a minimum trace width of 9.5 mm to restrict temperature rise to <20°C.
- Requirement B (Electrical Isolation): To prevent high-frequency switching noise from coupling into the analog feedback lines, the isolation clearance spacing must be at least 3.0 mm (complying with the safety clearance envelope for the switching voltage).
Observed Failure
The total physical routing channel available in this region of the board layout is strictly constrained to 11.5 mm due to mechanical enclosure boundaries.
Attempting to place a 9.5 mm trace alongside feedback routing with a 3.0 mm clearance requires a minimum spacing of 12.5 mm (excluding the width of the feedback trace itself). The routing engine was forced into an infinite solver loop, failing to find a valid layout and outputting:
[DRC-029] CONSTRAINT_VIOLATION: OVERLAP_ERROR
Required Space: 12.5 mm (Power Trace 9.5mm + Spacing 3.0mm)
Available Space: 11.5 mm (Enclosure limit)
Release Gate: LOCKED (Double conflict)Impact
The system could not compile manufacturing outputs. Compromising on either rule would result in:
- Reducing trace width: Trace runs hot (exceeding safety limits), risking thermal failure.
- Reducing spacing: Noise coupling on the feedback trace, causing driver control loop instability and signal degradation.
Trade-off Analysis & Decision Matrix
The engineering team conducted a structured design review to evaluate how to resolve the constraint overlap:
| Option | Thermal | Clearance | Cost | Result |
|---|---|---|---|---|
| Option A (Prioritize current capacity; reduce clearance to 1.5mm) | PASS (20°C rise) | FAIL (1.5mm < 3.0mm) | LOW | Rejected (High risk of feedback signal noise corruption) |
| Option B (Prioritize clearance; reduce trace width to 7.0mm) | FAIL (38°C rise) | PASS (3.0mm) | LOW | Rejected (Exceeds thermal safety envelope of board) |
| Option C (Stack-up modification: Increase copper weight to 2 oz) | PASS (22.5°C rise) | PASS (4.5mm) | MEDIUM | Selected (Satisfies both physical rules by altering volume parameters) |
Resolution
The team selected Option C. The PCB stack-up parameters were modified to specify 2 oz (70µm) copper thickness on inner layers (Layer 2 and Layer 3).
By doubling the copper thickness, the required trace width to carry 12A continuous within thermal limits was reduced from 9.5 mm to 5.2 mm (maintaining cross-sectional area). This left 6.3 mm of routing space. The power trace was routed at 5.2 mm, leaving 4.5 mm of electrical isolation clearance — which exceeded the 3.0 mm minimum requirement.
Verification
The layout was compiled with the updated stack-up parameters. ClaimGuard solvers re-evaluated both electrical spacing and current thermal parameters:
[SOLVER] Auditing Option C parameters...
Copper Weight: 2 oz (70µm)
Power Trace: 5.2 mm (Calc ΔT: 22.5°C -> PASS)
Clearance: 4.5 mm (Req: 3.0mm -> PASS)
[STATUS] All checks passed. Spacing and thermal limits are verified.
[STATUS] Release status: UNBLOCKEDLessons Learned
Multi-dimensional geometric constraints cannot be solved by simply compromising safety parameters. When physical boundaries create conflicts, solutions must be sought in spatial dimensions, such as modifying stack-up copper weight or altering dielectric thicknesses, rather than bypassing design constraints.